Coverart for item
The Resource Field-programmable logic and applications : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 : proceedings, Gordon Brebner, Roger Woods (eds.)

Field-programmable logic and applications : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 : proceedings, Gordon Brebner, Roger Woods (eds.)

Label
Field-programmable logic and applications : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 : proceedings
Title
Field-programmable logic and applications
Title remainder
11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 : proceedings
Statement of responsibility
Gordon Brebner, Roger Woods (eds.)
Title variation
FPL 2001
Creator
Contributor
Subject
Genre
Language
eng
Member of
Additional physical form
Also available via the World Wide Web. Abstracts available without subscription.
Cataloging source
DLC
Dewey number
621.39/5
Illustrations
illustrations
Index
index present
LC call number
TK7895.G36
LC item number
I357 2001
Literary form
non fiction
http://bibfra.me/vocab/lite/meetingDate
2001
http://bibfra.me/vocab/lite/meetingName
International Conference on Field-Programmable Logic and Applications
Nature of contents
bibliography
http://library.link/vocab/relatedWorkOrContributorDate
1963-
http://library.link/vocab/relatedWorkOrContributorName
  • Brebner, Gordon
  • Woods, Roger
Series statement
Lecture notes in computer science
Series volume
2147
http://library.link/vocab/subjectName
  • Field programmable gate arrays
  • Programmable array logic
Label
Field-programmable logic and applications : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 : proceedings, Gordon Brebner, Roger Woods (eds.)
Instantiates
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
volume
Carrier category code
  • nc
Carrier MARC source
rdacarrier
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Technology Trends and Adaptive Computing / M. J. Flynn and A. A. Liddicoat -- Prototyping Framework for Reconfigurable Processors / S. Sawitzki, S. Kohler and R. G. Spallek -- An Emulator for Exploring RaPiD Configurable Computing Architectures / C. Fisher, K. Rennie and G. Xing / [et al.] -- A New Placement Method for Direct Mapping into LUT-Based FPGAs / J. Abke and E. Barke -- fGREP -- Fast Generic Routing Demand Estimation for Placed FPGA Circuits / P. Kannan, S. Balachandran and D. Bhatia -- Macrocell Architectures for Product Term Embedded Memory Arrays / E. Lin and S. J. E. Wilton -- Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs / B. S. Goda, R. P. Kraft and S. R. Carlough / [et al.] -- Memory Synthesis for FPGA-Based Reconfigurable Computers / A. Kasat, I. Ouaiss and R. Vemuri -- Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic / S. J. Melnikoff, S. F. Quigley and M. J. Russell -- Implementation (Normalised) RLS Lattice on Virtex / F. Albu, J. Kadlec and C. Softley / [et al.] -- Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing / A. Amira, A. Bouridane and P. Milligan -- Static Profile-Driven Compilation for FPGAs / S. Cadambi and S. C. Goldstein -- Synthesizing RTL Hardware from Java Byte Codes / M. J. Wirthlin, B. L. Hutchings and C. Worth -- PuMA++: From Behavioral Specification to Multi-FPGA-Prototype / K. Harbich and E. Barke -- Secure Configuration of Field Programmable Gate Arrays / T. Kean -- Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm / M. McLoone and J. V. McCanny -- JBits Implementations of the Advanced Encryption Standard (Rijndael) / S. McMillan and C. Patterson -- Task-Parallel Programming of Reconfigurable Systems / M. Weinhardt and W. Luk -- Chip-Based Reconfigurable Task Management / G. Brebner and O. Diessel -- Configuration Caching and Swapping / S. Sudhir, S. Nath and S. C. Goldstein -- Multiple Stereo Matching Using an Extended Architecture / M. Arias-Estrada and J. M. Xicotencatl -- Implementation of a NURBS to Bezier Conversor with Constant Latency / P. N. Mallon, M. Boo and J. D. Bruguera -- Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems / S. A. Cuenca, F. Ibarra and R. Alvarez -- Processing Models for the Next Generation Network / J. Lawrence -- Tightly Integrated Placement and Routing for FPGAs / P. Kannan and D. Bhatia -- Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays / J. Karro and J. Cohoon -- Reconfigurable Router Modules Using Network Protocol Wrappers / F. Braun, J. Lockwood and M. Waldvogel -- Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware / Y. Ha, B. Mei and P. Schaumont / [et al.] -- The MOLEN [rho][mu]-Coded Processor / S. Vassiliadis, S. Wong and S. Cotofana -- Run-Time Optimized Reconfiguration Using Instruction Forecasting / M. Iliopoulos and T. Antonakopoulos -- CRISP: A Template for Reconfigurable Instruction Set Processors / P. Op de Beeck, F. Barat and M. Jayapala / [et al.] -- Evaluation of an FPGA Implementation of the Discrete Element Method / B. Carrion Schafer, S. F. Quigley and A. H. C. Chan -- Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers / A. Dandalis, V. K. Prasanna and B. Thiruvengadam -- A Reconfigurable Embedded Input Device for Kinetically Challenged Persons / A. Dollas, K. Papademetriou and N. Aslanides / [et al.] -- Bubble Partitioning for LUT-Based Sequential Circuits / F. Wolz and R. Kolla -- Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits / S. Singh and P. James-Roxby -- Placing, Routing, and Editing Virtual FPGAs / L. Lagadec, D. Lavenier and E. Fabiani / [et al.] -- Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver / L.-K. Ting, R. Woods and C. Cowan -- A Music Synthesizer for FPGA / T. Saito, T. Maruyama and T. Hoshino / [et al.] -- Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders / S. Sheidaei, H. Noori and A. Akbari / [et al.] -- Loop Tiling for Reconfigurable Accelerators / S. Derrien and S. Rajopadhye -- The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems / G. Sassatelli, L. Torres and J. Galy / [et al.] -- A n-Bit Reconfigurable Scalar Quantiser / O. Cadenas and G. Megson -- Real Time Morphological Image Contrast Enhancement in Virtex FPGA / J. Kasperek -- Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing / A. Simpson, J. Hunter and M. Wylie / [et al.] -- Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware / N. Voss and B. Mertsching -- The Evolution of Programmable Logic: Past, Present, and Future Predictions / B. Carter -- Dynamically Reconfigurable Cores / J. MacBeth and P. Lysaght -- Reconfigurable Breakpoints for Co-debug / T. Price and C. Patterson -- Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification / T. Wheeler, P. Graham and B. Nelson / [et al.] -- FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits / P. Civera, L. Macchiarulo and M. Rebaudengo / [et al.] -- A Generic Library for Adaptive Computing Environments / T. Neumann and A. Koch -- Generative Development System for FPGA Processors with Active Components / S. Ruhl, P. Dillinger and S. Hezel / [et al.] -- Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines / J. M. P. Cardoso and H. C. Neto -- System Level Tools for DSP in FPGAs / J. Hwang, B. Milne and N. Shirazi / [et al.] -- Parameterized Function Evaluation for FPGAs / O. Mencer, N. Boullis and W. Luk / [et al.] -- Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures / M. J. Wirthlin and B. McMurtrey -- A Digit-Serial Structure for Reconfigurable Multipliers / C. Visavakul, P. Y. K. Cheung and W. Luk -- FPGA Resource Reduction Through Truncated Multiplication / K. E. Wires, M. J. Schulte and D. McCarley -- Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures / J. Becker, N. Liebau and T. Pionteck / [et al.] -- An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars / C. Ciressan, E. Sanchez and M. Rajman / [et al.] -- Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach / J. Harkin, T. M. McGinnity and L. P. Maguire -- An Approach to Real-Time Visualization of PIV Method with FPGA / T. Maruyama, Y. Yamaguchi and A. Kawase -- FPGA-Based Discrete Wavelet Transforms System / M. Nibouche, A. Bouridane and F. Murtagh / [et al.] -- X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor / J. L. Nunez, C. Feregrino and S. Jones / [et al.] -- Arithmetic Operation Oriented Reconfigurable Chip: RHW / T. Yamauchi, S. Nakaya and T. Inuo / [et al.] -- Initial Analysis of the Proteus Architecture / M. Dales -- Building Asynchronous Circuits with JBits / E. Keller -- Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux / T. Lehmann and A. Schreckenberg -- A Reconfigurable Approach to Packet Filtering / R. Sinnappan and S. Hazelhurst -- FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding / R. Stefo, J. L. Nunez and C. Feregrino / [et al.] -- A Data Re-use Based Compiler Optimization for FPGAs / R. Subramanian and S. Pande -- Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware / M. Tommiska and J. Skytta -- A System on Chip for Power Line Communications According to European Home Systems Specifications / I. Urriza, J. I. Garcia-Nicolas and A. Sanz / [et al.]
Control code
47797446
Dimensions
24 cm
Dimensions
unknown
Extent
xv, 665 pages
Isbn
9783540424994
Isbn Type
(softcover : alk. paper)
Lccn
2001045763
Media category
unmediated
Media MARC source
rdamedia
Media type code
  • n
Other physical details
illustrations
Specific material designation
remote
Label
Field-programmable logic and applications : 11th International Conference, FPL 2001, Belfast, Northern Ireland, UK, August 27-29, 2001 : proceedings, Gordon Brebner, Roger Woods (eds.)
Publication
Bibliography note
Includes bibliographical references and index
Carrier category
volume
Carrier category code
  • nc
Carrier MARC source
rdacarrier
Content category
text
Content type code
  • txt
Content type MARC source
rdacontent
Contents
Technology Trends and Adaptive Computing / M. J. Flynn and A. A. Liddicoat -- Prototyping Framework for Reconfigurable Processors / S. Sawitzki, S. Kohler and R. G. Spallek -- An Emulator for Exploring RaPiD Configurable Computing Architectures / C. Fisher, K. Rennie and G. Xing / [et al.] -- A New Placement Method for Direct Mapping into LUT-Based FPGAs / J. Abke and E. Barke -- fGREP -- Fast Generic Routing Demand Estimation for Placed FPGA Circuits / P. Kannan, S. Balachandran and D. Bhatia -- Macrocell Architectures for Product Term Embedded Memory Arrays / E. Lin and S. J. E. Wilton -- Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs / B. S. Goda, R. P. Kraft and S. R. Carlough / [et al.] -- Memory Synthesis for FPGA-Based Reconfigurable Computers / A. Kasat, I. Ouaiss and R. Vemuri -- Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic / S. J. Melnikoff, S. F. Quigley and M. J. Russell -- Implementation (Normalised) RLS Lattice on Virtex / F. Albu, J. Kadlec and C. Softley / [et al.] -- Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing / A. Amira, A. Bouridane and P. Milligan -- Static Profile-Driven Compilation for FPGAs / S. Cadambi and S. C. Goldstein -- Synthesizing RTL Hardware from Java Byte Codes / M. J. Wirthlin, B. L. Hutchings and C. Worth -- PuMA++: From Behavioral Specification to Multi-FPGA-Prototype / K. Harbich and E. Barke -- Secure Configuration of Field Programmable Gate Arrays / T. Kean -- Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm / M. McLoone and J. V. McCanny -- JBits Implementations of the Advanced Encryption Standard (Rijndael) / S. McMillan and C. Patterson -- Task-Parallel Programming of Reconfigurable Systems / M. Weinhardt and W. Luk -- Chip-Based Reconfigurable Task Management / G. Brebner and O. Diessel -- Configuration Caching and Swapping / S. Sudhir, S. Nath and S. C. Goldstein -- Multiple Stereo Matching Using an Extended Architecture / M. Arias-Estrada and J. M. Xicotencatl -- Implementation of a NURBS to Bezier Conversor with Constant Latency / P. N. Mallon, M. Boo and J. D. Bruguera -- Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems / S. A. Cuenca, F. Ibarra and R. Alvarez -- Processing Models for the Next Generation Network / J. Lawrence -- Tightly Integrated Placement and Routing for FPGAs / P. Kannan and D. Bhatia -- Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays / J. Karro and J. Cohoon -- Reconfigurable Router Modules Using Network Protocol Wrappers / F. Braun, J. Lockwood and M. Waldvogel -- Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware / Y. Ha, B. Mei and P. Schaumont / [et al.] -- The MOLEN [rho][mu]-Coded Processor / S. Vassiliadis, S. Wong and S. Cotofana -- Run-Time Optimized Reconfiguration Using Instruction Forecasting / M. Iliopoulos and T. Antonakopoulos -- CRISP: A Template for Reconfigurable Instruction Set Processors / P. Op de Beeck, F. Barat and M. Jayapala / [et al.] -- Evaluation of an FPGA Implementation of the Discrete Element Method / B. Carrion Schafer, S. F. Quigley and A. H. C. Chan -- Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers / A. Dandalis, V. K. Prasanna and B. Thiruvengadam -- A Reconfigurable Embedded Input Device for Kinetically Challenged Persons / A. Dollas, K. Papademetriou and N. Aslanides / [et al.] -- Bubble Partitioning for LUT-Based Sequential Circuits / F. Wolz and R. Kolla -- Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits / S. Singh and P. James-Roxby -- Placing, Routing, and Editing Virtual FPGAs / L. Lagadec, D. Lavenier and E. Fabiani / [et al.] -- Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver / L.-K. Ting, R. Woods and C. Cowan -- A Music Synthesizer for FPGA / T. Saito, T. Maruyama and T. Hoshino / [et al.] -- Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders / S. Sheidaei, H. Noori and A. Akbari / [et al.] -- Loop Tiling for Reconfigurable Accelerators / S. Derrien and S. Rajopadhye -- The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems / G. Sassatelli, L. Torres and J. Galy / [et al.] -- A n-Bit Reconfigurable Scalar Quantiser / O. Cadenas and G. Megson -- Real Time Morphological Image Contrast Enhancement in Virtex FPGA / J. Kasperek -- Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing / A. Simpson, J. Hunter and M. Wylie / [et al.] -- Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware / N. Voss and B. Mertsching -- The Evolution of Programmable Logic: Past, Present, and Future Predictions / B. Carter -- Dynamically Reconfigurable Cores / J. MacBeth and P. Lysaght -- Reconfigurable Breakpoints for Co-debug / T. Price and C. Patterson -- Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification / T. Wheeler, P. Graham and B. Nelson / [et al.] -- FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits / P. Civera, L. Macchiarulo and M. Rebaudengo / [et al.] -- A Generic Library for Adaptive Computing Environments / T. Neumann and A. Koch -- Generative Development System for FPGA Processors with Active Components / S. Ruhl, P. Dillinger and S. Hezel / [et al.] -- Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines / J. M. P. Cardoso and H. C. Neto -- System Level Tools for DSP in FPGAs / J. Hwang, B. Milne and N. Shirazi / [et al.] -- Parameterized Function Evaluation for FPGAs / O. Mencer, N. Boullis and W. Luk / [et al.] -- Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures / M. J. Wirthlin and B. McMurtrey -- A Digit-Serial Structure for Reconfigurable Multipliers / C. Visavakul, P. Y. K. Cheung and W. Luk -- FPGA Resource Reduction Through Truncated Multiplication / K. E. Wires, M. J. Schulte and D. McCarley -- Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures / J. Becker, N. Liebau and T. Pionteck / [et al.] -- An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars / C. Ciressan, E. Sanchez and M. Rajman / [et al.] -- Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach / J. Harkin, T. M. McGinnity and L. P. Maguire -- An Approach to Real-Time Visualization of PIV Method with FPGA / T. Maruyama, Y. Yamaguchi and A. Kawase -- FPGA-Based Discrete Wavelet Transforms System / M. Nibouche, A. Bouridane and F. Murtagh / [et al.] -- X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor / J. L. Nunez, C. Feregrino and S. Jones / [et al.] -- Arithmetic Operation Oriented Reconfigurable Chip: RHW / T. Yamauchi, S. Nakaya and T. Inuo / [et al.] -- Initial Analysis of the Proteus Architecture / M. Dales -- Building Asynchronous Circuits with JBits / E. Keller -- Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux / T. Lehmann and A. Schreckenberg -- A Reconfigurable Approach to Packet Filtering / R. Sinnappan and S. Hazelhurst -- FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding / R. Stefo, J. L. Nunez and C. Feregrino / [et al.] -- A Data Re-use Based Compiler Optimization for FPGAs / R. Subramanian and S. Pande -- Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware / M. Tommiska and J. Skytta -- A System on Chip for Power Line Communications According to European Home Systems Specifications / I. Urriza, J. I. Garcia-Nicolas and A. Sanz / [et al.]
Control code
47797446
Dimensions
24 cm
Dimensions
unknown
Extent
xv, 665 pages
Isbn
9783540424994
Isbn Type
(softcover : alk. paper)
Lccn
2001045763
Media category
unmediated
Media MARC source
rdamedia
Media type code
  • n
Other physical details
illustrations
Specific material designation
remote

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